发明名称 MEMORY WIRING ARRANGEMENT WITH CHANGEABLE COMMON MODE REJECTION CIRCUIT LOOP
摘要 The electrical format of a common mode rejection digit circuit for a magnetic memory is changed for reading and writing memory operations by means of multilateral diode bridge switches. A memory word circuit is coupled through memory storage devices to a data digit circuit and two canceling digit circuits associated therewith. The sense of coupling to the canceling circuits is opposite to one another. During writing operations, the data circuit is operated with a canceling circuit which is coupled to the word circuit in opposite sense from the data circuit, and during reading the data circuit is operated with a canceling circuit which is coupled to the word circuit in the same sense as the data circuit to assure equality of opposed shuttle noises in the common mode rejection circuits.
申请公布号 US3633184(A) 申请公布日期 1972.01.04
申请号 USD3633184 申请日期 1969.07.17
申请人 BELL TELEPHONE LABORATORIES INC. 发明人 PHILIP A. HARDING;GEORGE D. KRAFT
分类号 G11C7/02;G11C11/06;(IPC1-7):G11C7/02 主分类号 G11C7/02
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