| 摘要 |
A phase locked loop comprising a phase comparator (32) for receiving an incoming signal with which it is desired to lock, a loop filter (30) to process a current error signal, and an integrator (22, 34) to adjust the output to account for the error, wherein the phase comparator, loop filter and integrator are formed from digital logic elements. The phase comparator (32) may be implemented as a two's complement subtractor, the loop filter (30) as a barrel shifter and the integrator (22, 34) as an accumulator register. The phase locked loop is used to generate an output signal (50) synchronised with an input signal (SI) by providing a plurality of phase shifted signals using a delay line or a shift register and selecting one of said phase shifted signals as the output signal according to a phase comparison between the selected signal and the input signal. The DPLL may be advantageously used for recovery of clock signals in digital data communications systems, in particular in Manchester coded Ethernet data.
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