发明名称 PROCESSOR
摘要 <p>PROBLEM TO BE SOLVED: To improve the throughput by performing conditional branching operation according to a state signal based upon the execution of an instruction described right before a conditional branch instruction. SOLUTION: A flag decoder 9 generates a control signal according to an instruction Q outputted by an instruction memory 2 and an operation flag signal F' outputted by a flag register 8 and supplies the control signal (e) to a control terminal of an instruction decoder 3. The instruction decoder 3 executes the branch instruction or conditional branch instruction by varying a control signal (j) and a control signal (k) according to the inputted control signal (e). Therefore, the decoding of the flag decoder 9 is completed in the time from a rise of a system clock signalϕto a rise of a clock signalϕto perform conditional branch operation by a flag change by operation right before it. Consequently, the operation speed can be made fast.</p>
申请公布号 JPH10161873(A) 申请公布日期 1998.06.19
申请号 JP19960319657 申请日期 1996.11.29
申请人 TOSHIBA CORP 发明人 SHIRAISHI MIKIO;SAITO MASAKI;OKUDA YUJI
分类号 G06F1/06;G06F9/32;G06F9/38;G06F15/78;(IPC1-7):G06F9/38 主分类号 G06F1/06
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