Recording clock generating device and method thereof

摘要

Crosstalk between tracks, land prepit leakage, and effects of recording power modulation can cause the wobble signal period to change irregularly, producing jitter in the recording clock derived by frequency multiplying the wobble signal. This problem is resolved by a recording clock generating circuit having an arrangement to average the wobble signal period, a timer for generating a rectangular wave with substantially the same period as the average period, and a frequency multiplying PLL for multiplying timer output. The period averaging arrangement in particular determines the approximate average period at every wobble period and reflects the phase difference between the wobble signal and timer in the timer setting to improve recording clock stability.