| 摘要 |
A SRAM circuit and a driving method thereof are provided to enable to fabricate a low power semiconductor memory, by reducing leakage power and switching power together. In an SRAM circuit, a first NMOS transistor(MN1), a first PMOS transistor(MP1), a second NMOS transistor(MN2) and a second PMOS transistor(MP2) are included between a driving voltage terminal and a ground terminal. Gate terminals of the first NMOS transistor and the first PMOS transistor are connected to a second node, and drain terminals of the first NMOS transistor and the first PMOS transistor are connected to a first node, in order to form one inverter. Gate terminals of the second NMOS transistor and the second PMOS transistor are connected to the first node and drain terminals of the second NMOS transistor and the second PMOS transistor are connected to the second node, in order to form another inverter. Two inverters are cross-coupled, and a first transfer switch and a second transfer switch driven by a third node are connected to the first node and the second node. A source-line driver is included between the memory cell and the ground terminal, and comprises a fifth PMOS transistor(MP5) and a fifth NMOS transistor(MN5) dynamically controlling a source line voltage of the memory cell with a voltage value from a driving voltage to a ground voltage. Gates of the fifth NMOS transistor and the fifth PMOS transistor are controlled by a fourth node.
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