| 发明名称 |
Capacitively coupled input buffer |
| 摘要 |
A buffer circuit comprising a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse corresponding to a hold time of the first buffer stage such that the buffer circuit detects a transition of the input signal during the hold time. |
| 申请公布号 |
US9374093(B2) |
申请公布日期 |
2016.06.21 |
| 申请号 |
US201414152177 |
申请日期 |
2014.01.10 |
| 申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
Pelley Perry H.;Ramaraju Ravindraraj |
| 分类号 |
H03B1/00;H03K3/00;H03K19/0185 |
主分类号 |
H03B1/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A buffer circuit comprising:
a capacitor, the capacitor comprising a first terminal and a second terminal, an input signal being coupled to the first terminal; a first buffer stage coupled to the second terminal of the capacitor such that the input signal is capacitively coupled to the first buffer stage, the first buffer stage comprising a data hold time; and, a pulse generator coupled to control the first buffer stage, the pulse generator being configured to generate a control pulse within the data hold time of the first buffer stage such that the second terminal of the capacitor is restored to a level corresponding to a level of the input signal during the data hold time. |
| 地址 |
Austin TX US |
