OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU

摘要

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

主权项

1. A multi core processor comprising:
at least four cache regions; a least eight cores, wherein a core of the at least eight cores comprises: a plurality of thermal sensors to collect sense thermal data for the core, and a plurality of performance counters to count architectural events occurring within the core, at least one of the performance counter to count completed instructions; and a power management control unit to: manage power usage of at least a core of the multi core processor per core basis based on a value wherein the value includes at least one of available power and/or thermal readings from one or more of the plurality of thermal sensors and/or a count of architectural events counted by the performance counters; and to adjust a frequency of the at least one core; and to set a turbo mode based on the at least one available a power budget.