发明名称 Triple well isolated diode and method of making
摘要 A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well.
申请公布号 US9391159(B2) 申请公布日期 2016.07.12
申请号 US201213438600 申请日期 2012.04.03
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Cheng Chih-Chang;Chu Fu-Yu;Liu Ruey-Hsin
分类号 H01L29/66;H01L29/06;H01L29/861;H02M3/156 主分类号 H01L29/66
代理机构 Hauptman Ham, LLP 代理人 Hauptman Ham, LLP
主权项 1. A semiconductor device comprising: a boost converter circuit, wherein the boost converter circuit comprises: a triple well isolated diode comprising: a substrate having a first conductivity type;a buried layer in the substrate, wherein the buried layer has a second conductivity type opposite to the first conductivity type;an epi-layer over the substrate and the buried layer, wherein the epi-layer has the first conductivity type;a first well in the epi-layer, wherein the first well has the second conductivity type;a second well in the epi-layer and surrounding sides of the first well, wherein the second well has the first conductivity type, and a portion of the second well forms an interface with the buried layer;a third well formed in the epi-layer and surrounding sides of the second well, wherein the third well has the second conductivity type, a surface of the third well closest to the substrate is coplanar with a surface of the second well closest to the substrate, and the third well contacts the second well; anda deep well in the epi-layer extending beneath the first well to electrically connect to the second well on opposite sides of the first well, wherein the deep well has the first conductivity type, and the deep well is separated from the third well; andan anode, wherein the second well and the third well are configured to electrically connect to the anode; anda cathode, wherein the first well is configured to electrically connect to the cathode.
地址 Hsinchu TW