发明名称 Programming algorithm for improved flash memory endurance and retention
摘要 A method applies a first set of consecutive pulses to flash memory cells in one or more flash memory devices to program the flash memory cells using a first pulse increment, a voltage of each consecutive pulse of the first set being incremented by the first pulse increment. On receiving an indication that the flash memory cells are partially programmed after the first set of consecutive pulses is applied, the first pulse increment is adjusted to an adjusted pulse increment based on a number of program/erase cycles associated with the flash memory cells. A second set of consecutive pulses to the flash memory cells is then applied using the adjusted pulse increment, a voltage of each consecutive pulse of the second set being incremented by the adjusted pulse increment.
申请公布号 US9514823(B2) 申请公布日期 2016.12.06
申请号 US201514794741 申请日期 2015.07.08
申请人 HGST Technologies Santa Ana, Inc. 发明人 Melik-Martirosian Ashot
分类号 G11C16/04;G11C16/10;G11C11/56 主分类号 G11C16/04
代理机构 McDermott Will & Emery LLP 代理人 McDermott Will & Emery LLP
主权项 1. A method for programming flash memory, comprising: applying a first set of consecutive pulses to flash memory cells in one or more flash memory devices to program the flash memory cells to a predetermined target voltage level using a first pulse increment, a magnitude of each consecutive pulse of the first set being incremented by the first pulse increment, a width of each consecutive pulse of the first set being set to a first pulse width; receiving, after the first set of consecutive pulses are applied, a program failed status returned by the one or more flash memory devices, indicating that the programming of the flash memory cells to the predetermined target voltage level is incomplete; adjusting, without user interaction and in response to the program failed status, the first pulse increment to an adjusted pulse increment; and applying a second set of consecutive pulses to the flash memory cells to program the flash memory cells to the predetermined target voltage level using the adjusted pulse increment, a magnitude of each consecutive pulse of the second set being incremented by the adjusted pulse increment, a width of each consecutive pulse of the second set being set to a second pulse width, wherein the second pulse width is different than the first pulse width.
地址 Santa Ana CA US