发明名称 Address storage circuit and memory and memory system including the same
摘要 A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.
申请公布号 US9514798(B2) 申请公布日期 2016.12.06
申请号 US201414297311 申请日期 2014.06.05
申请人 SK Hynix Inc. 发明人 Song Choung Ki;Jang Ji Eun;Yoon Seok Cheol
分类号 G11C7/00;G11C11/406;G11C11/408 主分类号 G11C7/00
代理机构 IP & T Group LLP 代理人 IP & T Group LLP
主权项 1. A memory, comprising: a plurality of word lines wherein one or more memory cells are coupled to individual word lines; an address storage unit configured to store an input address at a random time, wherein the input address corresponding to an active command at random time; a target address generation unit configured to generate a target address by adding or subtracting a set value to or from an address stored in the address storage unit; and a control unit configured to activate a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines corresponding to the target address when performing a refresh operation, wherein the one or more target word lines comprise one or more word lines adjacent to the word line corresponding to the address stored in the address storage unit.
地址 Gyeonggi-do KR