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发明名称
Full adder
摘要
A full adder is constituted with complementary MOS FETs, wherein delay time of adding time and carry signal delay time are shortened as a result of reduced number of stages of signal processing gates.
申请公布号
US4601007(A)
申请公布日期
1986.07.15
申请号
US19840573718
申请日期
1984.01.25
申请人
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
发明人
UYA, MASARU;KANEKO, KATSUYUKI
分类号
G06F7/50;G06F7/501;G06F7/503;G06F7/507;(IPC1-7):G06F7/50
主分类号
G06F7/50
代理机构
代理人
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