| 摘要 |
An access to a CGA I/O port (16) or an EGA I/O port (18) by a CPU (9) is detected by an NMI generator (7). The NMI generator (7) then supplies an interrupt signal to the CPU (9). The CPU (9) accesses an I/O monitor RAM (5), and detects the accessed I/O port. The CPU (9) refers to a CGA/EGA display flag (21), and when the accessed I/O port is different from a display mode set in the flag, the CPU sets a display mode corresponding to the accessed I/O port in the CGA/EGA display flag (21). The CPU (9) sets, in a display timing register (25), a display timing parameter corresponding to the display mode set in the flag (21). |
