发明名称 POWER MOS CONTROL CIRCUIT
摘要 PURPOSE:To prevent occurrence of EMI due to a transient phenomenon and destruction of the control circuit due to kick back by interposing a discharge control MOS transistor(TR) in series between a gate of a power MOSTR and a charge extraction MOSTR. CONSTITUTION:When a gate potential Vc of a power MOSTR MA is decreased by the extraction of a gate charge by a charge extraction MOSTRM1, a current Iout from the TRMA to a load L is decreased and an output voltage Vout is decreased. When the gate potential Vc is too much decreased, a gate-source voltage Vgs is reduced, the quantity of conduction is reduced and an output current lout is decreased. Thus, the output voltage Vout is reduced, the voltage Vgs is again extended, the quantity of conduction is increased, the output current Iout is increased and then the potential Vc is again reduced due to the increase in the quantity of conduction. The output voltage Vout is interrupted through the repetition above. Thus, the output current Iout when the power MOSTRMA is switched from ON to OFF is interrupted while tracing a changing locus where EMI or a transient phenomenon such as kick back is minimized.
申请公布号 JPH0661826(A) 申请公布日期 1994.03.04
申请号 JP19920212752 申请日期 1992.08.10
申请人 HITACHI LTD;HITACHI TOBU SEMICONDUCTOR LTD 发明人 WATANABE KENJI;NUNOKAWA YASUHIRO;HORIUCHI SHUICHI
分类号 H03K17/08;H03K17/687;H03K17/695 主分类号 H03K17/08
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