METHOD AND APPARATUS FOR INCREASING THE TIME AVAILABLE FOR REFRESH FOR 1-T SRAM COMPATIBLE DEVICES

摘要

In a burst read transaction, all the data in the burst transaction is prefetched from a DRAM memory into the read buffer in one memory cycle. The DRAM array can therefore be refreshed while the burst read data is sequentially transferred from the read buffer to the I/Q interface. In a burst write transaction, multiple burst write data values are written to a write buffer over multiple I/O cycles. This burst write data is not simultaneously retired to the DRAM array until the next write transaction. As a result, the DRAM array is only engaged in the burst write transaction for one memory cycle. The DRAM array can therefore be refreshed during one or more of the remaining three I/O cycles.