发明名称 |
Method of forming metal connection elements in integrated circuits |
摘要 |
A method of forming metal connection elements in integrated circuits formed on adjacent areas of a wafer includes forming a conductive seed layer on a substrate of the wafer. A first mask covers the integrated circuits and leaves exposed areas of the seed layer overlying predetermined scribe lines used for separation of the integrated circuits. Using the seed layer as a cathode, a metal is deposited by an electrochemical process on exposed areas of the seed layer. The first mask is removed and a second mask is formed, leaving predetermined areas of the seed layer exposed. Using the seed layer as a cathode a metal is deposited on the exposed predetermined areas by an electrochemical process. The second mask is then removed. Connection elements of uniform thickness throughout the substrate are produced with the use of a very thin seed layer.
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申请公布号 |
US2002111015(A1) |
申请公布日期 |
2002.08.15 |
申请号 |
US20020068549 |
申请日期 |
2002.02.06 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
NAPOLITANO MARIO |
分类号 |
H01L21/288;H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/288 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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