发明名称 Method to reduce power in a computer system with bus master devices
摘要 A system memory accessed by a bus master controller is set as non-cacheable. A bus master status bit is not set for any bus master controller transfer cycles with the non-cacheable memory while the a system processor is in a low power state.
申请公布号 GB0420421(D0) 申请公布日期 2004.10.20
申请号 GB20040020421 申请日期 2003.02.25
申请人 INTEL CORP 发明人
分类号 G06F1/32;G06F12/08 主分类号 G06F1/32
代理机构 代理人
主权项
地址