发明名称 |
High-speed differential logic to CMOS translator architecture with low data-dependent jitter and duty cycle distortion |
摘要 |
Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.
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申请公布号 |
US7301370(B1) |
申请公布日期 |
2007.11.27 |
申请号 |
US20040852272 |
申请日期 |
2004.05.24 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
HANNA SHERIF;LANDRY GREG J.;REFALO ALAN;VIJAYARAGHAVAN JEYENTH |
分类号 |
H03K19/094;H03K19/0175 |
主分类号 |
H03K19/094 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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