<p>A semiconductor memory device storing information by using a change in resistance is provided with a sense amplifier (SA), a data latch (LATR) holding the output of the sense amplifier, and a data latch control circuit (LATRC) controlling the latch timing of the data latch in such a manner that it differs in a reading operation from in a verifying operation. For example, the latch timing in the reading operation can determine the states of a memory cell having the highest resistance value (Rsmax) in a first state (a set state) and the memory cell having the lowest resistance value (Rrmin) in a second state(a reset state) by the sense amplifier with equal level margins. In the verifying operation to the second state, the latch timing can discriminate the memory cell having the lowest resistance value or above in the second state from the second state.</p>
