发明名称 |
Reference line and bit line structure for 3D memory |
摘要 |
A 3D NAND flash memory includes even and odd stacks of conductive strips. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars include even and odd semiconductor films on the data storage structures connected at the bottom ends so that the semiconductor films can be thin films having a U-shaped current path. An even pad connected to the even semiconductor film and an odd pad connected to the odd semiconductor film are disposed over the even and odd stacks respectively. A segment of a reference line is connected to the even pad, and an inter-level connector is connected to the odd pad. A segment of a bit line comprises an extension contacting the inter-level connector. |
申请公布号 |
US9412752(B1) |
申请公布日期 |
2016.08.09 |
申请号 |
US201514861377 |
申请日期 |
2015.09.22 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
Yeh Teng-Hao;Hu Chih-Wei;Jiang Yu-Wei |
分类号 |
H01L27/115;H01L27/105 |
主分类号 |
H01L27/115 |
代理机构 |
Haynes Beffel & Wolfeld LLP |
代理人 |
Haynes Beffel & Wolfeld LLP |
主权项 |
1. A memory device, comprising:
first and second stacks of conductive strips having sidewalls; data storage structures on the sidewalls of the first and second stacks; first and second vertical channel films on the data storage structures on the sidewalls of the first and second stacks, each first vertical channel film including a first pad over the first stack on an upper end of the first vertical channel film, and each second vertical channel film including a second pad over the second stack on an upper end of the second vertical channel film, the first and second vertical channel films being connected at bottom ends; a first level of patterned conductors overlying the first and second stacks, the patterned conductors in the first level comprising a segment of a reference line and an inter-level connector, the segment of the reference line connected to the first pad, the inter-level connector connected to the second pad; a second level of patterned conductors over the first level, the patterned conductors in the second level comprising a segment of a bit line, the segment of the bit line including an extension contacting the inter-level connector; and a multilayered insulating structure over the first level, the multilayered insulating structure comprising a first insulating film, a second insulating film and a third insulating film, the extension comprising a fin within the first and second insulating films. |
地址 |
Hsinchu TW |