Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift

摘要

A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

主权项

1. A method of operation of a memory controller device that controls a memory device, the method comprising:
generating, at the memory controller device, a write strobe having a write-strobe phase; receiving, from the memory device, read data accompanied by a read strobe having a read-strobe phase; and adjusting the write-strobe phase in response to the read-strobe phase.