Performance estimation using configurable hardware emulation

摘要

An integrated circuit can include a processor operable to execute program code and an Intellectual Property (IP) modeling block. The IP modeling block can include a first port through which the IP modeling block receives first modeling data and a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation. The first IP modeling block also can include a power emulation circuit. The power emulation circuit is configured to consume a variable amount of power as specified by the first modeling data received via the first port.

主权项

1. An integrated circuit comprising:
a processor operable to execute program code; a first intellectual property (IP) modeling block comprising:
a first port through which the first IP modeling block receives first modeling data comprising a power profile;a second port coupled to the processor through which the first IP modeling block communicates with the processor during emulation; anda power emulation circuit configured to consume a variable amount of power during emulation as programmed by the power profile of the first modeling data;wherein the first IP modeling block is a circuit block implemented in programmable circuitry of the integrated circuit by loading configuration data and is programmed with the modeling data to mimic a segment of program code selected for hardware acceleration without performing a function of the segment of program code.