| 摘要 |
The main memory of a data processing system comprises a plurality of modules, each with four memory planes (60), each storing 16k 39-bit words (32 bits data plus 7 parity bits). Write data is received from a controller on a write data bus (WDO-38) and read data goes to the controller on a read data bus (RDO-38). Up to 16 modules can be selected by fourselecting bits (MOD SELO-3) which are compared by a comparator (66) with the module's own address (MODO-3). The memory planes are accessed in sequence using seven address bits (ADDRO-5, J ADR 6) latched in address latches (67) in conjunction with a row address strobe (RAS) and a column address strobe (CAS) which strobe in row and column addresses sequentially from the latches to complete the selection of a single word to be written or read. Control logic (65) controls selection of write and read operations in response to signals (LDIN, LDOUT), and refreshing in response to a refresh signal (REFRESH). |
