| 摘要 |
<p>PURPOSE:To reduce an input capacitance so as to attain high speed and simultaneously, to recover a clock free from delay difference even if the delay difference is caused to some extent between two phases of input by receiving the input only with an NMOS transistor and operating this clock driver circuit differ-entially. CONSTITUTION:A positive phase clock input terminal 1A is connected to the gate electrodes of the NMOS transistors N3, N4, and a negative phase clock input terminal 1B is connected to the gate electrodes of the NMOS transistors N5, N6. Besides, PMOS transistors P3, P6 and P4, P5 are connected to the drains of the transistors N3, N5 respectively. Besides, the input terminal of an inverter circuit 12B is connected to the drain electrodes of the transistors N6, P6 and its output terminal is connected to a negative phase output terminal 2B. Besides, the input terminal of the inverter circuit 12A is connected to the drain electrodes of the transistors N4, P4 and its output terminal is connected to a positive phase clock output terminal 2A. Therefore, even if the weakening of waveform is caused in the input terminal 1A, waveform phase difference is absorbed since differential operation is performed in the vicinity of a threshold.</p> |
