| 摘要 |
<p>PURPOSE:To continuously generate and supply a normal synchronizing signal to an exchange main body regardless of the occurrence of abnormality of a network clock or a fault in the current or standby system. CONSTITUTION:Respective circuit units of the current system and the standby system are newly provided with internal clock generators 13a and 13b, network abnormality detecting circuits 14a and 14b, and selectors 16a and 16b. If the abnormality of a network clock ECK is detected by network abnormality detecting circuits 14a and 14b, the input clock to PLL circuits 11a and 11b is switched from the network clock ECK to an internal clock ICE by selectors 16a and 16b. Hereafter, reference clocks BCKa and BCRb are generated in PLL circuits 11a and 11b synchronously with the internal clock ICK, and frame synchronizing signals FSSa and FSSb and synchronizing clock SCKa and SCKb are generated in synchronizing signal generators 12a and 12b based on these reference clocks BCKa and BCKb.</p> |
