发明名称 CHECKING SYSTEM FOR ADDRESS DISCRIMINATION CIRCUIT
摘要 <p>PURPOSE:To surely detect that an error is generated in a circuit for finding an address by comparing the respective outputs of a simultaneous comparator circuit and an address decoding part. CONSTITUTION:The relation between the addresses an the values of VPI/VCI is stored in a VPI/VCI table 3, a latch circuit 3 extracts VPI/VCI from cells on a cell highway 1 to be latched and the simultaneous comparator circuit 4 simultaneously compares the output of the circuit 2 with the entired contents of the table 3. Then, when the circuit 4 outputs >=2 coincidence signals, an address discrimination part 10 outputs an erroneous encoded signal corresponding to the discordant signal. Since an address decoder 20 for receiving the encoded signal surely decodes and outputs only one signal, when the circuit 4 outputs >=2 coincidence signals, the >=2 signals and the one signal of the decoder 20 are compared and an error checking part 30 surely detects discordance and transmits an error signal.</p>
申请公布号 JPH0662033(A) 申请公布日期 1994.03.04
申请号 JP19910220180 申请日期 1991.08.30
申请人 FUJITSU LTD;FUJITSU KYUSHU COMMUN SYST CO LTD 发明人 FUKUDA NAOKI;YOSHIMURA SHUJI;KAKUMA SATORU
分类号 H04M11/00;H04L12/28;H04L12/70;(IPC1-7):H04L12/48 主分类号 H04M11/00
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