| 摘要 |
A frequency control device comprises, in the form of a phase-locked loop, a phase comparator, a filter, an oscillator producing a local clock signal and two divide-by-M frequency dividers. The dividers receive the local clock signal whose frequency is slaved to N times the frequency of a master clock signal, with M<N, and are looped to the inputs of the comparator. A first of the dividers is reinitialized at the frequency of the master clock signal. A load circuit loads the most-significant-bit stages of a counter included in the first divider with a binary word added to binary elements stored in most-significant-bit stages of a counter included in the second divider, after a resetting of the second divider following a general initialization of the device.
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