| 摘要 |
A technique for providing testable core-cell based integrated circuits is described whereby a boundary-scan like technique is employed, but not limited to the external pins (bond pads) of an integrated circuit. An interior boundary-scan path is provided for all peripheral signals of core cells and logic blocks which are not connected to pins of the integrated circuit. This technique provides complete controllability and observability of each core cell and/or logic block on an integrated circuit die, while remaining compatible with test techniques designed into the core cells, and remaining fully compatible with external boundary scan techniques. Method and apparatus are described.
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