Circuit and method for generating a clock signal

摘要

A clock generator circuit which produces a clock signal which may have an adjustable steady state duty cycle and which has the same frequency as a crystal frequency. The clock generator circuit includes a drive circuit coupled to the crystal which converts the first signal to a clock signal, and a duty cycle control circuit which generates a feedback signal to cause the duty cycle to automatically change to the steady state duty cycle. The clock generator circuit of the present invention may also include an output pad for allowing a measuring instrument to determine the duty cycle.