ANALOG CAPACITOR HAVING AT LEAST 3 LAYERS OF HIGH-K DIELECTRIC LAYERS AND METHOD OF FABRICATING THE SAME

摘要

An analog capacitor having at least 3 high-k dielectric layers is provided to optimize a voltage coefficient of capacitance and a leakage current characteristic while having a high-k dielectric layer by making high-k dielectric layer with an excellent voltage coefficient of capacitance come in contact with plates and by interposing a high-k dielectric layer capable of preventing a leakage current between the high-k dielectric layers. A lower plate(11) is formed. An upper plate(15) corresponding to the lower plate is formed. At least three high-k dielectric layers(13) are interposed between the lower and upper plates, including a bottom dielectric layer(13a) in contact with the lower plate, a top dielectric layer(13c) in contact with the upper plate, and a middle dielectric layer(13b) interposed between the bottom and top dielectric layers. Each of bottom and top dielectric layers is a high dielectric layer having a small absolute value of the coefficient of a quadratic term of a voltage coefficient as compared with the middle dielectric layer. The middle dielectric layer is a high dielectric layer having a small leakage current as compared with the bottom and top dielectric layers, respectively.