| 摘要 |
Disclosed is a semiconductor memory device including a plurality of banks, a plurality of data input/output terminals, control signal terminals, address signal terminals, and at least one or a plurality of virtual chips, each of which has the banks grouped together, thereby being operable as one independent chip. Each of the data input/output terminals are allocated in dedicated manner to the one virtual chip or one of the plurality of virtual chips. The control signal terminals and the address signal terminals are shared among the one or the plurality of virtual chips.
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