MEMORY CONTROLLER AND METHOD OF DATA BUS INVERSION USING AN ERROR DETECTION CORRECTION CODE

摘要

Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

主权项

1. A memory controller comprising:
write circuitry to transmit write data along a databus to a memory device, the write circuitry including:
a write error detection correction (EDC) encoder to generate first error information associated with the write data, anddata bus inversion (DBI) circuitry to conditionally invert data bits associated with each of the write data words based on threshold criteria; and read circuitry to receive read data from the memory device, the read data corresponding to the write data words, the read circuitry including
a read EDC encoder to generate second error information associated with the received read data, andlogic to evaluate the first and second error information, and conditionally reverse-invert at least a portion of the read data based on the evaluating.