Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality

摘要

Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.

主权项

1. A processor comprising:
a first register comprising a first plurality of data fields, wherein each of the first plurality of data fields in the first register is to store a second plurality of bits; a first destination register comprising a third plurality of data fields corresponding to the first plurality of data fields, wherein each of the third plurality of data fields in the first destination register is to store a count of a number of most significant contiguous bits set to zero for a corresponding data field of the first plurality of data fields; a decode stage to decode a first instruction specifying a vector leading zero count operation; and one or more execution units, responsive to the decoded first instruction, to:
read the values of each of the data fields in the first register;for each data field of the first plurality of data fields in the first register, count the number of most significant contiguous bits set to zero, andstore the count as a value in a corresponding data field of the third plurality of data fields in the first destination register.