发明名称 Clock generator, communication device and sequential clock gating circuit
摘要 The present invention discloses a clock generator comprising: an oscillator operable to generate a reference clock; a multi-phase clock generating circuit operable to generate a plurality of output clocks of the same frequency but different phases according to the reference clock and stop or start outputting the output clocks according to a power control signal; a sequential clock gating circuit operable to sequentially stop or start outputting a plurality of gated clocks according to a gate control signal and maintain an output cycle number relation between the gated clocks even though the multi-phase clock generating circuit stops and then starts outputting the output clocks; and a clock operation control circuit operable to provide the power control signal and the gate control signal.
申请公布号 US9501088(B2) 申请公布日期 2016.11.22
申请号 US201514720056 申请日期 2015.05.22
申请人 REALTEK SEMICONDUCTOR CORPORATION 发明人 Chiang Chih-Jung;Tseng Shun-Te;Liu Kai-Yin;Lin Jian-Ru
分类号 G06F1/10;G06F1/08 主分类号 G06F1/10
代理机构 WPAT, P.C., Intellectual Property Attorneys 代理人 WPAT, P.C., Intellectual Property Attorneys ;King Anthony
主权项 1. A clock generator comprising: an oscillator operable to generate a reference clock; a multi-phase clock generating circuit, coupled to the oscillator, operable to generate a plurality of output clocks according to the reference clock, and operable to stop or start outputting the output clocks according to a power control signal in which the output clocks have the same frequency but different phases; a sequential clock gating circuit, coupled to the multi-phase clock generating circuit, operable to sequentially stop or start outputting a plurality of gated clocks according to a gate control signal and the plurality of output clocks, and operable to maintain an output cycle number relation between the gated clocks after the multi-phase clock generating circuit stopped and then starts outputting the output clocks; and a clock operation control circuit, coupled to the multi-phase clock generating circuit and the sequential clock gating circuit, operable to provide the power control signal and the gate control signal.
地址 Hsinchu TW
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