| 摘要 |
A standard pseudo-random number generator comprises a shift register with a plurality of XOR feedback paths from the last stage to the first and selected intermediate stages. This invention provides a larger generator by concatenating four such registers 9a to 9d in series. The feedback pattern of each register is a maximum length polynomial, and the registers are all of different lengths (67, 63, 64, and 65 bits) such that their periods are all coprime. The largest register is first for maximum randomness. The number of feedback paths of each register is an even integer approximately equal to either one third or two thirds of the number of stages in the register. The generator may be used in a VLSI chip including a core logic area performing an operational function to apply a test pattern to the core logic. For receiving the output of the core logic in response to the test patterns, the chip may include an check sum output register 8 in the form of a cyclic ring with an initial, relatively small portion in the form of a linear feedback shift register. The generator and check sum output may form part of test circuitry in a VLSI chip, being configured partly from I/0 cells and partly from dummy cells, the I/0 cells normally operating as input and output to the core logic of the chip. |
