| 摘要 |
A multi-streaming processor has a plurality of streams (103) for streaming one or more instruction threads, set of functional resources (105) for processing instructions from streams, and interrupt handler logic (407). The logic detects (403) and maps (409) interrupts and exceptions into one or more specific streams (401). In some embodiments one interrupt and exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped into one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to determine the mapping. Interrupts may be external interrupts (405) generated by devices external to the processor software (internal) interrupts (411) generated by active streams, or conditional, based on variables. After interrupts are acknowledged streams to which interrupts or exceptions are mapped are vectored to appropriate service routines. In a synchronous method no vectoring occurs until all streams to which an interrupt is mapped acknowledge the interrupt. |
