Asynchronous arbitration device and microcontroller including such an arbitration device

摘要

The device has a detection unit detecting request from central processing unit and universal serial bus controller to access a memory space. A selection unit generates a selection signal assuming two states. Clock units generate clock signals to enable a static random access memory (SRAM) to serve the requests from the unit and controller if the selection signal assumes the two states, respectively. A reset unit generates reset signals to erase the requests from the unit and controller, respectively, after it is served. The selection signal assumes one state if a single detected request comes from the unit or if two requests are detected concurrently, and assumes another state if the request comes from the controller or if one of the two concurrently detected requests is already served. An independent claim is also included for a microcontroller comprising an arbitration device.