发明名称 Wafer level packages and methods of fabrication
摘要 A wafer level package formed on an integrated circuit chip having bondpads and a fabrication method therefor is disclosed. The wafer level package comprises at least one first, second and third separation layer having at least one first and second conductive layer formed in-between the separation layers. The at least one first conductive layer is formed on the at least one first separation layer and is coupled to the bondpads. The at least one second conductive layer is formed on the at last one second separation layer wherein the at least one second conductive layer is electrically coupled to the at least one first conductive layer. The at least one third separation layer allows solder to be attached to the at least one second conductive layer for electrically coupling the solder to the bondpads. A chip ground plane is laid in the integrated circuit chip for providing a ground to the at least one first conductive layer and the solder.
申请公布号 US7189594(B2) 申请公布日期 2007.03.13
申请号 US20040938239 申请日期 2004.09.10
申请人 AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH 发明人 KRIPESH VAIDYANATHAN;WONG WAI KWAN;ROTARU MIHAI DRAGOS;CHAI TAI CHONG;IYER MAHADEVAN KRISHNA
分类号 H01L21/50;H01L21/44;H01L21/48;H01L23/48;H01L23/52 主分类号 H01L21/50
代理机构 代理人
主权项
地址