发明名称 Process for controlled collapse chip connection - wherein ball-limiting metallurgy is etched in the presence of lead@-tin@ solder bumps
摘要 <p>A method is disclosed for removing metal layers from the surface of a wafer in the presence of a Pb/Sn solder bump, comprising the steps (a) removing a first metal layer (15) from the surface by exposing it to a first etchant, wherein a protective layer (18) is formed on the solder bump (17), (b) removing a second metal layer (14) from the surface of the wafer by exposing it to a second etchant, wherein at least a portion of the protective layer remains on the Pb/Sn solder bump after exposure to the second etchant, and (c) removing the protective layer from the solder bump by exposing the wafer to a third etchant.</p>
申请公布号 DE19581952(B4) 申请公布日期 2007.08.30
申请号 DE1995181952 申请日期 1995.12.18
申请人 INTEL CORPORATION 发明人 CRAFTS, DOUGLAS E.;MURALI, VENKATESAN;LEE, CAROLINE S.
分类号 H01L21/60 主分类号 H01L21/60
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