发明名称 |
High density memory array for low power application |
摘要 |
A phase change memory cell includes a MOS select transistor having a gate coupled to a word line, and a source and drain region coupled between first and second bit lines, respectively. A first phase change element is coupled between the first bit line and the source region of the MOS select transistor. A method of reading a selected cell in the array is provided by evaluating a body effect impact of a state of the phase change element associated with the selected cell on a MOS select transistor.
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申请公布号 |
US2007217318(A1) |
申请公布日期 |
2007.09.20 |
申请号 |
US20060378201 |
申请日期 |
2006.03.17 |
申请人 |
NIRSCHL THOMAS;HAPP THOMAS |
发明人 |
NIRSCHL THOMAS;HAPP THOMAS |
分类号 |
G11B3/00 |
主分类号 |
G11B3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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