System for synchronizing modules in an integrated circuit in mesochronous clock domains

摘要

This synchronization system is intended to synchronize modules (TX, RX) in an integrated circuit, in particular a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. This system comprises first latch means (5) for latching and delivering data in synchronism with the first clock signal and second latch means (6) for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals ( strobe_W, strobe_R ) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.