| 摘要 |
The invention relates to data processing hardware for generating holograms, in particular for image display applications. We describe a hardware error diffusion calculation system for performing an error diffusion quantisation of a hologram. The system comprises address and data buses for a first, hologram memory block 610 storing data representing pixels of said hologram; for a second, error memory block 608 storing an error matrix representing errors in quantising said hologram; for a third, diffusion weights memory block 606 storing a set of diffusion weights for said error diffusion calculation; and a plurality of error diffusion processor blocks 602 a-h each coupled to said address and data buses, each being configured for sequential processing of a spatial region of said hologram. A said processor block includes a pixel address generator to generate a sequence of pixel addresses for a said spatial region for processing by the processor block and an error diffusion calculation block coupled to said pixel address generator and to said address and data buses to perform an error diffusion calculation for a pixel of said hologram identified by a said pixel address. Spatial regions processed by said processor blocks overlap and each of said processor blocks has a different start pixel address such that said processor blocks are able to perform error diffusion calculations with respective error diffusion calculation blocks on different pixels of the hologram in parallel. The error diffusion quantization process may be performed concurrently with hologram data generation by pipelining a first system generating hologram data and a second system quantizing the hologram data using error diffusion as per the invention. |
