| 摘要 |
In a data processing unit, improvement of the writing speed and efficiency of demodulated data from demodulating means into the buffer memory is achieved. As solving means thereof, writing of data demodulated in the demodulating means into the buffer memory is continuously performed after waiting for arrival of data of the same kind. Therefore, upon transfer of the demodulated data from the demodulating circuit to a temporary storage sub-means within the bus controller which controls access to the buffer memory, the kind of data of the next demodulated data is also transmitted.
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