INTER-LEVEL DIELECTRIC LAYER IN REPLACEMENT METAL GATES AND RESISTOR FABRICATION

摘要

Embodiments in accordance with the present invention include a method of fabricating a semiconductor device including forming a first dummy gate in an active area on a first portion of a semiconductor device, wherein the first dummy gate includes undoped amorphous silicon. A second dummy gate and a third dummy gate are formed on a second portion of the semiconductor device, wherein the second dummy gate and the third dummy gate include undoped amorphous silicon. A filling material is deposited on the semiconductor device, where the filling material is doped amorphous silicon, and a chemical-mechanical polishing process is performed on the filling material.

主权项

1. A method of fabricating a semiconductor device, the method comprising:
forming a first dummy gate in an active area on a first portion of a semiconductor device, wherein the first dummy gate includes undoped amorphous silicon; forming a second dummy gate and a third dummy gate on a second portion of the semiconductor device, wherein the second dummy gate and the third dummy gate include undoped amorphous silicon; depositing a filling material on the semiconductor device, wherein the filling material is doped amorphous silicon; and performing a chemical-mechanical polishing process (CMP) on the filling material.