Power management for in-memory computer systems

摘要

According to one embodiment, a method for power management of a compute node including at least two power-consuming components is provided. A power capping control system compares power consumption level of the compute node to a power cap. Based on determining that the power consumption level is greater than the power cap, actions are performed including: reducing power provided to a first power-consuming component based on determining that it has an activity level below a first threshold and that power can be reduced to the first power-consuming component. Power provided to a second power-consuming component is reduced based on determining that it has an activity level below a second threshold and that power can be reduced to the second power-consuming component. Power reduction is forced in the compute node based on determining that power cannot be reduced in either of the first or second power-consuming component.

主权项

1. A method for power management of a compute node comprising at least two power-consuming components, the method comprising:
determining, by a power capping control system of the compute node, a power consumption level of the compute node; comparing, by the power capping control system, the power consumption level to a power cap; and based on determining that the power consumption level is greater than the power cap:
reducing power provided to a first power-consuming component of the compute node based on determining that the first power-consuming component has an activity level below a first threshold and that power is reducible to the first power-consuming component, wherein the first power-consuming component is an active memory device comprising a plurality of memory stacks associated with hub chips comprising processing elements that form lanes and reducing power provided to the first power-consuming component comprises turning off one or more of the lanes;reducing power provided to a second power-consuming component of the compute node based on determining that the second power-consuming component has an activity level below a second threshold and that power is reducible to the second power-consuming component, wherein the second power-consuming component is a multi-core processing chip; andforcing a power reduction in the compute node based on determining that power cannot be reduced in either of the first or second power-consuming component; and performing power shifting between the active memory device and the multi-core processing chip by:
comparing a number of required lanes to a number of turned-on lanes;based on determining that the number of required lanes is greater than the number of turned-on lanes, that the power consumption level is greater than or equal to the power cap, and that power is reducible to the multi-core processing chip, reducing power to the multi-core processing chip; andbased on determining that the number of required lanes is greater than the number of turned-on lanes and that the power consumption level is less than the power cap, turning on an extra lane.