发明名称 TFT ARRANGEMENT STRUCTURE
摘要 The present invention provides a TFT arrangement structure, comprising a first thin film transistor (T1) and a second thin film transistor (T2) controlled by the same control signal line; the first active layer (SC1) of the first thin film transistor (T1) and the second active layer (SC2) of the second thin film transistor (T2) are at different layers, and positioned to stack up in space, and the first source (S1) and the first drain (D1) of the first thin film transistor (T1) contact the first active layer (SC1), and the second source (S2) and the second drain (D2) of the second thin film transistor (T2) contact the second active layer (SC2); the bottom gate layer (Bottom Gate) of the first thin film transistor (T1) is positioned under the first active layer (SC1), and the top gate layer (Top Gate) of the second thin film transistor (T2) is above the second active layer (SC2). The TFT arrangement structure can reduce the space of the circuit arrangement to increase the flexibility of the circuit arrangement and satisfy the demands of the narrow frame and high resolution to the display panel.
申请公布号 US2016315104(A1) 申请公布日期 2016.10.27
申请号 US201514770089 申请日期 2015.05.22
申请人 Shenzhen China Star Optoelectronics Technology Co. Ltd. 发明人 Han Baixiang;Shi Longqiang
分类号 H01L27/12;H01L29/786;H01L29/49;H01L29/22 主分类号 H01L27/12
代理机构 代理人
主权项 1. A TFT arrangement structure, comprising a first thin film transistor and a second thin film transistor controlled by the same control signal line; the first thin film transistor comprises a bottom gate layer, a first active layer, a first source and a first drain, and the second thin film transistor comprises a second active layer, a second source, a second drain and a top gate layer; the first active layer and the second active layer are at different layers, and positioned to stack up in space, and the first source and the first drain contact the first active layer, and the second source and the second drain contact the second active layer; the bottom gate layer is positioned under the first active layer, and the top gate layer is above the second active layer, and both the bottom gate layer and the top gate layer are electrically coupled to the control signal line to respectively control on and off of the first thin film transistor and the second thin film transistor.
地址 Shenzhen, City CN