发明名称 FAULT DETECTING SYSTEM
摘要 PURPOSE:To present the fault detecting system which does not define the operational not-coincidence of each arithmetic circuit as a fault according to asynchronous signals concerning the fault detecting system of the duplex arithmetic circuits. CONSTITUTION:An arithmetic stepping circuit 7 is provided to operate respective duplex arithmetic circuits 1 and 2 only for arbitrary clocks, and a means is provided to step one arithmetic circuit only for (n) clocks while stopping the operation of the other arithmetic circuit when non-coincidence is detected between the arithmetic circuits 1 and 2 or to step one arithmetic circuit only for (m)(>n) clocks while stopping the operation of the other arithmetic circuit. When coincidence is detected by operating only one or the other among the arithmetic circuits 1 and 2 by the means, the stop is canceled and when non- coincidence is detected in the both cases, it is recognized as the fault. 3,4: interruption signal/timer signal, 5: comparator circuit, 6: clock preparing circuit, I: fault, II: announcement to host device.
申请公布号 JPH04247531(A) 申请公布日期 1992.09.03
申请号 JP19910013099 申请日期 1991.02.04
申请人 FUJITSU LTD 发明人 TAKAHASHI HIROSHI;ISHIHARA KENJI
分类号 G06F7/00;G06F7/38;G06F11/18 主分类号 G06F7/00
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