发明名称 DYNAMIC TYPE LOGIC CIRCUIT
摘要 <p>PURPOSE:To decrease the operating current of the dynamic type logic circuit by suppressing the number of precharging times of the dynamic type logic circuit. CONSTITUTION:The precharge signal line of an X decoder 120 is formed by using a latch output signal line 191 synchronizing a decoding line 131 which is the output signal line of a Y decoder 130 at the timing of a 2nd clock signal line 161 in a latch circuit 190, a sequencer start signal line 111 which is inputted to a sequencer 110 and a 1st clock signal line 181.</p>
申请公布号 JPH04248196(A) 申请公布日期 1992.09.03
申请号 JP19910007562 申请日期 1991.01.25
申请人 NEC CORP 发明人 MIYAZAKI TAKASHI
分类号 G11C17/18;H03K19/177 主分类号 G11C17/18
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