| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a digital quadrature demodulator which has less fixed deterioration and has advantageous power consumption, a circuit scale and a price in high speed signal transmission. <P>SOLUTION: The demodulator includes A/D converters 100, 110 for receiving intermediate frequency signals and quantizing them with clock signals 20, 21 each having a frequency S/T and a phase difference of T/2S; an interpolation circuit 210 for compensating for an error from an ideal time point of the quantization timing of the A/D converter 110; a delay circuit 200 for delaying the output of the A/D converter 100 by the processing time of the interpolation circuit 210; a sign inverting circuit 300 for inverting the output of the delay circuit 200; a sign inverting circuit 310 for inverting the output of the interpolation circuit 210; and a selection circuit 400 for distributing the output of the delay circuit 200, the output of the interpolation circuit 210, and outputs of the sign inverting circuits 300, 310 to an in-phase output 50 or a quadrature output 60. <P>COPYRIGHT: (C)2004,JPO |
