Methods and apparatus for MOS capacitors in replacement gate process

摘要

Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

主权项

1. An apparatus, comprising:
an isolation region in a semiconductor substrate defining a first region and a second region of the substrate; a high-k metal gate device formed in the first region proximal to the isolation region, the high-k metal gate device comprising a high-k gate dielectric and a metal gate; a first polysilicon gate MOS capacitor and a second polysilicon gate MOS capacitor formed in the second region proximal to the isolation region, each of the first polysilicon gate MOS capacitor and the second polysilicon gate MOS capacitor comprising a gate dielectric and a polysilicon gate, the gate dielectric and the high-k gate dielectric having different material compositions, wherein a first edge of the first polysilicon gate MOS capacitor is spaced apart from a corresponding second edge of the second polysilicon gate MOS capacitor by a minimum pitch, and wherein the minimum pitch is determined by processing limitations for forming metal gates in the apparatus; and an interlayer dielectric layer over the substrate, wherein the interlayer dielectric layer contacts a sidewall of the first polysilicon gate MOS capacitor and a sidewall of the high-k metal gate device.