发明名称 |
PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS |
摘要 |
Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path. |
申请公布号 |
EP2976770(B1) |
申请公布日期 |
2016.10.19 |
申请号 |
EP20140727682 |
申请日期 |
2014.05.02 |
申请人 |
QUALCOMM INCORPORATED |
发明人 |
CHAI, CHIAMING;GE, SHAOPING;LILES, STEPHEN, EDWARD;GARG, KUNAL |
分类号 |
G11C11/412;G11C7/10;G11C7/12;G11C11/419 |
主分类号 |
G11C11/412 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|